(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of electrically isolating active regions on the surface of a semiconductor substrate thereby replacing the use of Shallow Trench Isolation regions.
(2) Description of the Prior Art
Semiconductor devices that are created on the surface of a substrate are electrically isolated from each other using techniques that are well established and that have been used extensively in the art. Three of the best-known techniques used for this purpose are Localized Oxidation of Silicon (LOCOS), poly buffered LOCOS and the use of Shallow Trench Isolation (STI) regions.
Current semiconductor progress depends to a large extent on a continued effort of micro-miniaturization of devices and device features that results in improved device performance and increased device density. This continued shrinkage of device dimensions presents new problems of device design and manufacturing. One of these problems is the requirement to provide an efficient and reliable process for the separation of active devices for the current miniaturized scale. One method previously used is the LOCOS process. The LOCOS process depends on the use of a temporary patterned nitride layer, this layer of nitride is used as a protective or resistant layer that covers the future active areas during the subsequent field oxidation process for forming CMOS gate structures. The industry provides numerous examples of efficient application of the LOCOS process with alternate approaches to achieve device isolation such as the Selective Polysilicon Oxidation (SEPOX) method.
The processing sequence for creating LOCOS isolation regions is as follows: an oxidation layer, generally silicon nitride, is deposited over a pad oxide overlying a silicon substrate. The pad oxide is a thin thermal oxide, which allows better adhesion between the nitride and the silicon substrate and acts as a stress relaxation layer during field oxidation. The nitride and oxide layers are etched to leave openings exposing portions of the silicon substrate where the local oxidation will take place thereby differentiating these regions from the regions in the surface of the substrate into which the active devices are to be formed. A boron channel-stop layer is ion implanted into the isolation regions. The field oxide is grown within the openings by placing the substrate in an oxidation environment, generally in steam at a high temperature such as 1100 degrees C. The portions of the silicon substrate not covered by the oxidation barrier oxidize to form thermal silicon in these portions while oxidation is masked from the active regions by the oxidation barrier. The nitride and pad oxide layers are removed completing the local oxidation of the silicon substrate. LOCOS field oxide is generally formed to a sufficient thickness such that a conductor placed over the LOCOS field oxide will not convert the underlying channel when biased to the maximum circuit voltage. The LOCOS process however suffers from the occurrence of the so-called bird""s beak. Adequate cushioning between the silicon nitride and the silicon substrate requires the presence of a layer of pad oxide of considerable thickness. This however brings with it that the layer of nitride becomes less effective as an oxidation mask thereby allowing lateral oxidation to occur in the surface of the substrate. This lateral oxidation is referred to at the bird""s beak effect and is detrimental to the requirements of sub-miniaturization since the bird""s beak reaches under and into regions that are being defined as active device regions, thereby limiting the smaller dimensions that can be assigned to these regions.
The disadvantages of LOCOS can be summarized as follows:
the bird""s beak structure encroaches into the device active area
the pre-implanted channel stop dopant re-distributes during the high temperature that is associated with field oxide growth. Redistribution of channel stop dopant primarily affects the active area periphery causing problems known as narrow-width defects
the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topographical disparities cause planarity problems which become severe as circuit critical dimension shrink
thermal oxide growth is significantly thinner in small field regions (that is field regions of small lateral dimensions) relative to large field regions.
An alternate approach to defining active regions in the surface of a substrate is the use of Shallow Trench Isolation (STI) regions. STI regions can be made using a variety of methods. For instance, one method is to use Buried Oxide (BOX) isolation combined with shallow trenches. The method involves creating trenches in the surface of the substrate that delineate the active regions in the surface of the substrate and filling the trenches with a chemical vapor deposition (CVD) of silicon oxide (SiO2) . The SiO2 is etched back or Chemically Mechanically Polished (CMP) yielding a planar surface of the STI regions. The shallow trenches etched for the BOX process are anisotropically plasma etched into the silicon substrate and are typically between 0.5 and 0.8 micrometer (pm) deep. STI regions are typically formed around active device regions to a depth between 4,000 and 20,000 Angstrom.
Another approach in forming STI""s is to deposit silicon nitride on thermally grown oxide. After deposition of the nitride, a shallow trench is etched into the substrate using a mask. A layer of oxide is then deposited into the trench so that the trench forms an area of dielectric insulation, which acts to isolate the devices in a chip and thus reduces cross talk and leakage currents between active devices. The excess deposited oxide is removed and the trench planarized to prepare for the next level of metallization. The silicon nitride is provided to the silicon to prevent polishing of the masked silicon oxide of the device.
Disadvantages of the application of STI regions can be summarized as follows:
forming of STI""s involves etching in silicon, which creates dangling bonds at the surface of the created trenches. It is believed that dangling bonds and an irregular grain structure form in the silicon substrate near the wells of the trench. Such dangling bonds may promote trapping of charge carriers within the active areas of an operating transistor. As a result, charge carrier mobility may be hindered, and the output current of the transistor may decrease to an amount at which optimum device performance is unattainable
during subsequent anneal processing (e.g. thermal oxidation for gate oxide formation), the irregular grain may provide migration avenues through which oxygen atoms can pass from the field oxide to the active area near the edges of field oxide. Oxygen atoms that are present in active areas of the silicon may function as electron donors. Thus, inversion of silicon may occur in subsequently formed p-type active areas near the walls of the isolation trench. Further, the edge of a device may not conduct as much current as the interior portion of the device. Therefore, more charge to the gate of a transistor may be required to invert the channel than if no inversion occurred, causing threshold voltage, Vt, to shift undesirably from its design specifications.
In a subsequent processing steps, the semiconductor topography may undergo a high temperature anneal to activate impurity species in the active areas and to annihilate crystalline defect damage to the substrate. Unfortunately, impurity species, such as boron, in the active area may undergo diffusion into the isolation region when subjected to high temperatures. As a result, the threshold voltage in the isolation regions may decrease. Thus, migration of impurities into the isolation region may lead to current inadvertently flowing between active areas, defeating the purpose of having the trench isolation in the first place. It is therefore desirable to develop a technique for forming a trench isolation structure between active regions in which problems related to dangling bonds and irregular grain structure in the active area are alleviated. Such a technique is required to inhibit charge carriers and oxygen donors from being entrapped in the active areas. Yet further, it is desirable that impurity species be prevented from migrating into the trench isolation structure so that current leakage between active areas may be inhibited
the required silicon nitride and silicon substrate etch are difficult processing steps, and
the trench oxide deposition is an expensive High Density Plasma (HDP) step.
U.S. Pat. No. 4,412,868 (Brown et al.) shows a method comprising: (1) form isolation oxide on substrate (2) etch AA openings (3) deposit Si in AA openings. This patent has an additional O2 I/I step, but appears to show all the steps of the invention. This may raise an obvious rejection by the PTO.
U.S. Pat. No. 4,929,566 (Beitman) shows a process including (1), (2) and (3).
U.S. Pat. No. 5,443,992 (Risch et al.) shows a process for epitaxily growing a Si in opening in an isolation layer. This is close.
U.S. Pat. No. 5,234,861 (Roisen at al.) teaches a process of growing Si in a trench of isolation oxide.
U.S. Pat. No. 4,592,792 (Coroy Jr. et al.) teaches a process to (1) form isolation ox on substrate (2) etch AA openings (3) deposit Si in AA openings.
A principle objective of the invention is to provide a method for defining active regions in the surface of a substrate that is simple and readily integratable into a high speed, high volume semiconductor manufacturing environment.
Another objective of the invention is to provide a method for defining active regions in the surface of a substrate that can be used for the creation of semiconductor devices in the era of sub-micron and deep sub-micron device features.
In accordance with the objectives of the invention a new method is provided for the definition and delineation of active regions in the surface of a semiconductor substrate. A layer of pad oxide is grown on the surface of the substrate, the layer of pad oxide is patterned and etched whereby the pad oxide remains in place over areas where the isolation regions are to be created. The underlying silicon substrate is in this manner exposed; the regions of the silicon substrate that are exposed are the regions of the substrate where active devices are to be created. The exposed surface of the substrate is cleaned; the openings in the layer of pad oxide are selectively filled with a deposition of epitaxial silicon. The created structure is heat treated to improve the interface between the patterned and etched layer of pad oxide and the deposited epitaxial silicon. The created pattern of pad oxide can now be used as regions of field isolation over the surface of the substrate.